
PIC18F6585/8585/6680/8680
DS30491C-page 350
2004 Microchip Technology Inc.
REGISTER 24-5:
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
REGISTER 24-6:
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1
U-0
R/P-1
MCLRE
—
ECCPMX
CCP2MX
bit 7
bit 0
bit 7
MCLRE: MCLR Enable bit(1)
1
= MCLR pin enabled, RG5 input pin disabled
0
= RG5 input enabled, MCLR disabled
bit 6-2
Unimplemented: Read as ‘0’
bit 1
ECCPMX: CCP1 PWM outputs P1B, P1C mux bit (PIC18F8X8X devices only)(2)
1
= P1B, P1C are multiplexed with RE6, RE5
0
= P1B, P1C are multiplexed with RH7, RH6
bit 0
CCP2MX: CCP2 Mux bit
In Microcontroller mode:
1
= CCP2 input/output is multiplexed with RC1
0
= CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X8X devices only):
1
= CCP2 input/output is multiplexed with RC1
0
= CCP2 input/output is multiplexed with RB3
Note 1: If MCLR is disabled, either disable low-voltage ICSP or hold RB5/PGM low to
ensure proper entry into ICSP mode.
2: Reserved for PIC18F6X8X devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
R/P-1
U-0
R/P-1
U-0
R/P-1
DEBUG
—
—LVP
—STVREN
bit 7
bit 0
bit 7
DEBUG: Background Debugger Enable bit
1
= Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0
= Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.
bit 6-3
Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1
= Low-voltage ICSP enabled
0
= Low-voltage ICSP disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1
= Stack full/underflow will cause Reset
0
= Stack full/underflow will not cause Reset
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state